--- src/hotspot/os_cpu/bsd_ppc/orderAccess_bsd_ppc.hpp.orig	2026-04-13 11:00:19 UTC
+++ src/hotspot/os_cpu/bsd_ppc/orderAccess_bsd_ppc.hpp
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
+ * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -23,66 +23,5 @@
  *
  */
 
-#ifndef OS_CPU_BSD_PPC_VM_ORDERACCESS_BSD_PPC_HPP
-#define OS_CPU_BSD_PPC_VM_ORDERACCESS_BSD_PPC_HPP
-
-// Included in orderAccess.hpp header file.
-
-#ifndef PPC64
-#error "OrderAccess currently only implemented for PPC64"
-#endif
-
-// Compiler version last used for testing: gcc 4.1.2
-// Please update this information when this file changes
-
-// Implementation of class OrderAccess.
-
-//
-// Machine barrier instructions:
-//
-// - sync            Two-way memory barrier, aka fence.
-// - lwsync          orders  Store|Store,
-//                            Load|Store,
-//                            Load|Load,
-//                   but not Store|Load
-// - eieio           orders  Store|Store
-// - isync           Invalidates speculatively executed instructions,
-//                   but isync may complete before storage accesses
-//                   associated with instructions preceding isync have
-//                   been performed.
-//
-// Semantic barrier instructions:
-// (as defined in orderAccess.hpp)
-//
-// - release         orders Store|Store,       (maps to lwsync)
-//                           Load|Store
-// - acquire         orders  Load|Store,       (maps to lwsync)
-//                           Load|Load
-// - fence           orders Store|Store,       (maps to sync)
-//                           Load|Store,
-//                           Load|Load,
-//                          Store|Load
-//
-
-#define inlasm_sync()     __asm__ __volatile__ ("sync"   : : : "memory");
-#define inlasm_lwsync()   __asm__ __volatile__ ("lwsync" : : : "memory");
-#define inlasm_eieio()    __asm__ __volatile__ ("eieio"  : : : "memory");
-#define inlasm_isync()    __asm__ __volatile__ ("isync"  : : : "memory");
-
-inline void   OrderAccess::loadload()   { inlasm_lwsync(); }
-inline void   OrderAccess::storestore() { inlasm_lwsync(); }
-inline void   OrderAccess::loadstore()  { inlasm_lwsync(); }
-inline void   OrderAccess::storeload()  { inlasm_sync();   }
-
-inline void   OrderAccess::acquire()    { inlasm_lwsync(); }
-inline void   OrderAccess::release()    { inlasm_lwsync(); }
-inline void   OrderAccess::fence()      { inlasm_sync();   }
-inline void   OrderAccess::cross_modify_fence_impl()
-                                        { inlasm_isync();  }
-
-#undef inlasm_sync
-#undef inlasm_lwsync
-#undef inlasm_eieio
-#undef inlasm_isync
-
-#endif // OS_CPU_BSD_PPC_VM_ORDERACCESS_BSD_PPC_HPP
+// Including inline assembler functions that are shared between multiple PPC64 platforms.
+#include "orderAccess_ppc.hpp"
